Voltage margin testing for proximity communication
US7979754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Sep 18, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49133
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.