Cost-benefit optimization for an airgapped integrated circuit
US7979824B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Nov 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method, apparatus and program product provide automated processes for determining the most cost-effective use of airgaps in a microchip. The performance gains realized by using airgaps for a given net or layer may be calculated. These improvements may be paired to a monetary cost associated with implementing the applicable airgaps at that net/layer. The paired benefit and cost of the airgap scenario may be compared to other possible airgap uses at other layers/nets to determine which airgaps provide the best improvement for the lowest cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.