Thin film transistor array panel and method for manufacturing the same
US7981737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2009 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Nov 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/466
Abstract
A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.