Methods of fabrication of channel-stressed semiconductor devices
US7981750B2 · kind B2 · utility
5Cited by
4References
23Claims
0Family size
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Key dates
| Filing date | Jun 13, 2008 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Aug 15, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
Abstract
In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.