Pixel array
US7982219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2009 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel array includes scan lines, data lines, and pixels. Each pixel arranged in the nth row includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In the first sub-pixel, a first gate and a first drain of a first transistor are connected to the (n−1)th scan line and a first pixel electrode, respectively. In the second sub-pixel, a second gate of a second transistor is connected to the nth scan line, and a second drain is connected to a second pixel electrode and a first source of the first transistor. In the third sub-pixel, a third gate of a third transistor is connected to the (n+1)th scan line, a third drain is connected to a third pixel electrode and a second source of the second transistor, and a third source is connected to one of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.