Method for reducing the reactive power requirement of a fundamental frequency clocked power supply side converter under no load and with low motor loading
US7983060B2 · kind B2 · utility
2Cited by
7References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Jun 12, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for reducing the idle current requirement of a base frequency clocked supply side converter (1) on idle and with low motor loads, provided with controllable semiconductors (T1,T2,T3,T4, T5,T6), wherein the base frequency clocking of the semiconductor switches (T1,T2,T3,T4,T5,T6) occurs depending on the desired direction of flow of power. A converter (1) for carrying out said method is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.