Macro-block level parallel video decoder
US7983342B2 · kind B2 · utility
9Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the decoded DCT coefficients, and multiple slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at the macro-block level. Also provided is a method for macro-block level video decoding in a parallel processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.