Clock data recovery circuit
US7983361B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 17, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock data recovery circuit. The clock data recovery circuit comprises a transmission line, a phase locked loop, a voltage controlled oscillator, a phase selector, and a D flip-flop. The transmission line receives an input signal. The phase locked loop receives the input signal via the transmission line and a reference clock and generates a first clock signal. The voltage controlled oscillator receives the input signal via the transmission line and a control voltage from an internal node of the phase locked loop, and generates a clock signal. The phase selector receives the input signal via the transmission line and the clock signal from the voltage controlled oscillator, and generates a clock output signal. The D flip-flop receives the input signal via the transmission line and the clock output signal, and generates a data output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.