Programmable direct memory access controller having pipelined and sequentially connected stages
US7984204B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 13, 2008 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Jan 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.