Memory system
US7984232B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2008 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Mar 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial value generator which generates an initial value for every segment, an initial value shifter which shifts the initial value by N bits for every page address, a pseudo random number generator which generates a pseudo random number sequence by an M-sequence by using the initial value shifted N bits, and a random number adder which adds the pseudo random number sequence to the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.