System and method for random defect yield simulation of chip with built-in redundancy
US7984399B1 · kind B1 · utility
2Cited by
4References
16Claims
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Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Feb 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.