Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region

US7985644B1 · kind B1 · utility

Assignee

• PMC-Sierra, Inc. · US

Inventors

• Graeme B. Boyd · North Vancouver, CA
• William Michael Lye · Burnaby, CA
• Xun Cheng · Dublin, US

Key dates

• Filing date: Oct 27, 2009
• Grant date: Jul 26, 2011
• Expiry date: Oct 27, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.