Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices
US7986160B2 · kind B2 · utility
17Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2006 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | May 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.