Jitter attenuation with a fractional-N clock synthesizer
US7986190B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Jan 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.