Method for designing integrated circuit incorporating memory macro
US7986583B2 · kind B2 · utility
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4References
15Claims
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Key dates
| Filing date | Feb 11, 2009 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Aug 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design method whereby memory instances are assigned to memory macros integrated within an integrated circuit. A plurality of memory instances operating at the same operation frequency are assigned to a single memory macro. A frequency multiplier which receives a first clock signal is arranged to generate a second clock signal through frequency multiplication of the first clock signal, and feeds the second clock signal to the plurality of memory instances. A control circuit which selects the memory instances in synchronization is arranged with the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.