CMOS transceiver for communication system
US7986726B2 · kind B2 · utility
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7References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 3, 2005 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Oct 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/71362
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.