Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
US7987222B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1733
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.