Communications in a processor array
US7987340B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 19, 2004 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Feb 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.