Performance monitors in a multithreaded processor architecture
US7987345B2 · kind B2 · utility
4Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3476
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a plurality of execution units configured to execute, at least in part, a plurality of instruction threads; a plurality of performance monitors, each performance monitor being configured to collect performance information related to the execution of at least one instruction thread; a selected thread identifier configured to provide, during operation, the selection of at least one instruction thread; and a performance manager configured to filter, utilizing the selected thread, the information collected by the plurality of performance monitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.