Patent · US Active

Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher voltages

US7989308B2 · kind B2 · utility

0Cited by

9References

7Claims

0Family size

Assignee

X-FAB SEMICONDUCTOR FOUNDRIES GMBH · DE

Inventors

Ralf Lerner · Erfurt, DE
Uwe Eckoldt · Hohenfelden, DE
Thomas Oetzel · Iserlohn, DE

Key dates

Filing date	Apr 7, 2005
Grant date	Aug 2, 2011
Priority date	—
Expiry date	Aug 21, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76235
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.