Implementing vertical airgap structures between chip metal layers
US7989337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jul 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.