Semiconductor device with three-dimensional field effect transistor structure
US7989846B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET. The sources of the three-dimensional P-type FETs in the first and second logic gate circuits are joined to the first common source semiconductor layer. The sources of the three-dimensional N-type FETs in the first and second logic gate circuits are joined to the second common source semiconductor layer. The semiconductor layers of the three-dimensional P-type and N-type FETs in the first logic gate circuit are joined in their drain side, and The semiconductor layers of the three-dimensional P-type and N-type FETs in the second logic gate circuit are joined in their drain side. The dissipation of the FinFET can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.