Anti-fuse cell and its manufacturing process
US7989914B2 · kind B2 · utility
2Cited by
2References
45Claims
0Family size
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Key dates
| Filing date | Dec 23, 2005 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jul 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.