Fast dynamic register
US7990180B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Oct 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.