Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor
US7990304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Nov 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/548
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.