Semiconductor chip and semiconductor device
US7990747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jun 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.