Least significant bit page recovery method used in multi-level cell flash memory device
US7990765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Feb 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory device includes setting first through nth LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages included in the MLC flash memory, programming the first through xth LSB pages (x is a natural number that is larger than 2) included in an ith LSB page group (i is a natural number that is smaller than n), generating and storing an ith LSB parity page for the first through xth LSB pages, programming first through xth MSB pages which correspond to one LSB page from among the first through xth LSB pages, and recovering a jth LSB page, which are paired with a jth MSB page, using the ith LSB parity page corresponding to the ith LSB page group, when a power supply to the MLC flash memory is stopped during the programming of the jth MSB page (j is a natural number that is smaller than x).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.