Setting memory controller driver to memory device termination value in a communication bus
US7990768B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Aug 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.