Patent · US Active

Synchronizing processors when entering system management mode

US7991933B2 · kind B2 · utility

2Cited by

3References

17Claims

0Family size

Assignee

Dell Products L.P. · US

Inventors

Juan Francisco Diaz · Norcross, US
Dirie N. Herzi · Leander, US
Robert Volentine · Houston, US

Key dates

Filing date	Jun 25, 2008
Grant date	Aug 2, 2011
Priority date	—
Expiry date	Mar 2, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/385
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.