Implementation of one time programmable memory with embedded flash memory in a system-on-chip
US7991943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2007 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Oct 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.