Data slicer having an error correction device
US7992077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2007 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jun 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.