Via antenna fix in deep sub-micron circuit designs
US7994543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | May 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.