CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same
US7994553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Oct 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/225
Abstract
A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.