Techniques for phase interpolation
US7994837B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.