Circuit arrangement comprising a non-volatile memory cell and method
US7995367B2 · kind B2 · utility
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14References
16Claims
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Key dates
| Filing date | Apr 12, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.