Method for binary clock and data recovery for fast acquisition and small tracking error
US7995698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Feb 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.