Interrupt arbitration for multiprocessors
US7996595B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2009 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.