Device for misaligned atomics for a highly-threaded x86 processor
US7996632B1 · kind B1 · utility
7Cited by
10References
15Claims
0Family size
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Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jul 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.