Digital locked loop on channel tagged memory requests for memory optimization
US7996642B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jan 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for performing memory optimization. The method includes receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods where none of the read/write requests will be received; and performing opportunistic functions during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.