Asynchronous first in first out interface and operation method thereof
US7996704B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | May 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.