Defect management for a semiconductor memory system
US7996710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Feb 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.