Patent · US Active

Multi nodal computer system and method for handling check stops in the multi nodal computer system

US7996715B2 · kind B2 · utility

2Cited by

3References

7Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Karin Rebmann · Holzgerlingen, DE
Dietmar Schmunkamp · Schenefeld, DE
Tobias Webel · Eppelheim, DE
Thomas E. Gilbert · Waukesha, US
Timothy G. McNamara · Fishkill, US
Patrick J. Meaney · Poughkeepsie, US

Key dates

Filing date	Nov 5, 2008
Grant date	Aug 9, 2011
Priority date	—
Expiry date	May 21, 2029

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S707/99943
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.