Method and apparatus for low-pin-count scan compression
US7996741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jan 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.