Semiconductor device and manufacturing method thereof
US7999317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2009 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A p-type body region and an n-type buffer region are formed on an n− drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n− drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.