Power electronic package having two substrates with multiple semiconductor chips and electronic components
US7999369B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Dec 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.