Multistage chopper stabilized delta-sigma ADC with reduced offset
US7999710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/456
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.