ESD protection for field effect transistors of analog input circuits
US8000068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2008 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jun 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.