Self reset clock buffer in memory devices
US8000165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2008 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jan 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.