Configuring a multi-processor system
US8001266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Nov 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.