Methods and apparatus for reallocating addressable spaces within memory devices
US8001356B2 · kind B2 · utility
7Cited by
2References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2006 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jun 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.